MOD 13 Ch 3 Flashcards Preview

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Flashcards in MOD 13 Ch 3 Deck (65)
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1

2

What is the sign of operation for the X-OR gate?

⊕.

3

What will be the output of an X-OR gate when both inputs are HIGH?

Low (0).

4

A two-input X-OR gate will produce a HIGH output when the inputs are at what logic levels?

One or the other of the inputs must be HIGH, but not both at the same time.

5

What type of gate is represented by the output Boolean expression T ⊕R ?

Exclusive NOR (X-NOR).

6

What will be the output of an X-NOR gate when both inputs are LOW?

HIGH.

7

What advantage does a half adder have over a quarter adder?

The half adder generates a carry.

8

An X-OR gate may be used as what type of adder?

Quarter adder.

9

What will be the output of a half adder when both inputs are 1s?

Sum equals 0 with a carry of 1.

10

What type of adder is used to handle a carry from a previous circuit?

Full adder.

11

How many full adders are required to add four-digit numbers?

Four.

12

With the inputs shown below, what will be the output of S1, S2, and C2?

S1 = 1, S2 = 0 and C2 = 1.

13

What is the output of C1?

C1 = 0

14

What type of logic gates are added to a parallel adder to enable it to subtract?

X-OR gates.

15

How many of these gates would be needed to add a four-digit number?

Four.

16

In the add mode, what does the output of C2 indicate?

MSD of the sum.

17

In the subtract mode, a 1 at C0 performs what portion of the R’s complement?

Add 1 portion.

18

In the subtract mode, which portion of the problem is complemented?

Subtrahend.

19

What are R-S FFs used for?

Storing information.

20

How many R-S FFs are required to store the number 1001012?

Six.

21

For an R-S FF to change output conditions, the inputs must be in what states?

1 and 0, or opposite states.

22

How may R-S FFs be constructed?

By cross-coupling NAND or OR gates.

23

How many inputs does a T FF have?

One.3-45

24

What is the purpose of using T FFs?

To divide the input by 2

25

What are the inputs to a D FF?

Clock and data.

26

How long is data delayed by a D FF?

Up to one clock pulse.

27

What condition must occur to have a change in the output of a D FF?

A positive-going clock pulse.

28

What type of FF can be used as an R-S, a T, or a D FF?

J-K flip-flop.

29

What will be the output of Q if J is HIGH, PS and CLR are HIGH, and the clock is going negative?

Set, or HIGH (1).

30

Assume that K goes HIGH and J goes LOW; when will the FF reset?

When the clock pulse goes LOW.