What is the sign of operation for the X-OR gate?
What will be the output of an X-OR gate when both inputs are HIGH?
A two-input X-OR gate will produce a HIGH output when the inputs are at what logic levels?
One or the other of the inputs must be HIGH, but not both at the same time.
What type of gate is represented by the output Boolean expression T ⊕R ?
Exclusive NOR (X-NOR).
What will be the output of an X-NOR gate when both inputs are LOW?
What advantage does a half adder have over a quarter adder?
The half adder generates a carry.
An X-OR gate may be used as what type of adder?
What will be the output of a half adder when both inputs are 1s?
Sum equals 0 with a carry of 1.
What type of adder is used to handle a carry from a previous circuit?
How many full adders are required to add four-digit numbers?
With the inputs shown below, what will be the output of S1, S2, and C2?
S1 = 1, S2 = 0 and C2 = 1.
What is the output of C1?
C1 = 0
What type of logic gates are added to a parallel adder to enable it to subtract?
How many of these gates would be needed to add a four-digit number?
In the add mode, what does the output of C2 indicate?
MSD of the sum.
In the subtract mode, a 1 at C0 performs what portion of the R’s complement?
Add 1 portion.
In the subtract mode, which portion of the problem is complemented?
What are R-S FFs used for?
How many R-S FFs are required to store the number 1001012?
For an R-S FF to change output conditions, the inputs must be in what states?
1 and 0, or opposite states.
How may R-S FFs be constructed?
By cross-coupling NAND or OR gates.
How many inputs does a T FF have?
What is the purpose of using T FFs?
To divide the input by 2
What are the inputs to a D FF?
Clock and data.
How long is data delayed by a D FF?
Up to one clock pulse.
What condition must occur to have a change in the output of a D FF?
A positive-going clock pulse.
What type of FF can be used as an R-S, a T, or a D FF?
What will be the output of Q if J is HIGH, PS and CLR are HIGH, and the clock is going negative?
Set, or HIGH (1).
Assume that K goes HIGH and J goes LOW; when will the FF reset?
When the clock pulse goes LOW.