Exam: Question 2 Flashcards Preview

CS4052 Logic and Software Verification > Exam: Question 2 > Flashcards

Flashcards in Exam: Question 2 Deck (52)
Loading flashcards...
1

How do you specify real-world systems in PROMELA?

- define global variables with "#define"
- make proctypes for all processes that do logic
- add comms if needed
- add init process to start proctypes without active keyword

2

How do you specify real-world systems in PROMELA, using synchronous comms?

- define global variables with "#define"
- make proctypes for all processes that do logic
- add init process to start proctypes without active keyword
- set up (unidirectional) channels for each possible direction of data transfer
- set up mtype of possible message types
- set up a byte array to hold data
- add getting logic with ? and sending logic with !

3

How do you show whether a PROMELA system may livelock?

go through possible execution scenarios from initialisation and find if they may cause each other to infinitely compete for a resource but still perform some action or change state

4

What is livelock?

A livelock is similar to a deadlock, except that the states of the processes involved in the livelock constantly change with regard to one another, none progressing.

A real-world example of livelock occurs when two people meet in a narrow corridor, and each tries to be polite by moving aside to let the other pass, but they end up swaying from side to side without making any progress because they both repeatedly move the same way at the same time.

5

Which PROMELA construct can be used to show that between two send communication actions there is always another communication?

A trace. A trace or notrace declaration does not specify new behaviour but instead states a correctness requirement on existing behaviour in the remainder of the system.

6

How can you make a constraint in PROMELA to show that between two send communication actions there is always another communication?

An event trace declaration that specifies the correctness requirement that send operations on channel q1 alternate with receive operations on channel q2. It also checks that all send operations on q1 are (claimed to be) exclusively messages of type a and all receive operations on channel q2 are exclusively messages of type b. This is written as follows:

mtype = { a, b }; // message type
trace {
do
:: q1!a; q2?b
od
}

7

How can you show whether a PROMELA specification holds a constraint?

Consider different possible considerations to find whether or not any possible execution does not satisfy the constraint and use it as proof of counterexample; otherwise, it does holds.

8

What is weak fairness?

“Every process that is continuously enabled from a certain time instant onwards gets its turn infinitely often."

9

What is strong fairness?

“Every process that is enabled infinitely often gets its turn infinitely often."

10

What is unconditional fairness?

"Every process gets its turn infinitely often."

11

What is the difference between weak, strong, and unconditional fairness?

unconditional = processes always get turns infinitely often

strong = all processes enabled infinitely often get turns infinitely often

weak = all processes constantly enabled from a given time get turns infinitely often

12

What does it mean to check a PROMELA property under strong/weak fairness?

!

13

How do you write a PROMELA never claim to prove or disprove a LTL property?

!

14

How do you specify real-world systems in PROMELA, using asynchronous comms?

!

15

How can SPIN check for livelocks?

!

16

What does it mean for a PROMELA specification to not terminate correctly?

!

17

How do you show whether it is possible for a PROMELA specification to not terminate correctly?

!

18

How can SPIN be used to check whether it is possible for a PROMELA specification to not terminate correctly?

!

19

What is an alternating bit protocol?

!

20

How can you model the alternating bit protocol in PROMELA?

!

21

What is the PROMELA timeout statement?

!

22

What is the PROMELA timeout statement useful for?

!

23

How can you find a trace that matches a PROMELA spec?

!

24

What is a trace in SPIN?

!

25

What is a never claim in SPIN?

!

26

What is the difference between a trace and never claim in SPIN?

!

27

How do you express strong fairness in LTL?

!

28

How do you express weak fairness in LTL?

!

29

What can check an LTL property over a PROMELA specification under strong fairness?

!

30

What can check an LTL property over a PROMELA specification under weak fairness?

!