12 MIPS and High RISC microprocessors Flashcards Preview

EE20021 Digital systems design > 12 MIPS and High RISC microprocessors > Flashcards

Flashcards in 12 MIPS and High RISC microprocessors Deck (30)
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1
Q

A RISC (Reduced Instruction Set Computer) architecture employs:

A

small number of instructions (nowadays, this is not 100% accurate)

  • simple instructions that execute quickly
  • larger number of registers
  • operations are performed between registers
2
Q

RISC philosophy

A

RISC philosophy is about the use of elementary/lowlevelcomplexity instructions that execute quickly!

3
Q

The MIPS microprocessor is an example of a RISC architecture.

details

A
  • developed in the 1980s at Stanford University
  • implements a small and simple ISA
  • allows the implementation of pipelining
  • uses 32 general purpose registers of 32 bits width
4
Q

The MIPS microprocessor, which now belongs to MIPS Technologies Inc., has been successful and widely used in:

A

embedded systems

Nintendo and Sony products

Cisco Internet routers and switches

5
Q

MIPS register structure diagram?

A
6
Q

MIPS To refer to registers we can use the following notation:

A
  • R0, R1, …, R31 or
  • $0, $1, …, $31
7
Q

MIPS Some special registers are:

A
  • R0 has a value of zero
  • R29 to R31 are use for subroutines or function calls
8
Q

MIPS Other register that are not part of the register file:

A

Program Counter (PC)

9
Q

MIPS Register addressing By convention we use:

A

$t:<register> indicates temporary result ($t5)</register>

$s:<register> indicates operation result ($s7)</register>

10
Q

MIPS microprocessor, overview of specific and struct values for the general purpose registers.

A

MIPS microprocessor does not enforce a specific and strict use for the general purpose register, except for register R0. Nowadays, there is a convention for the use of registers and this is employed by compilers and simulators.

11
Q

MIPS uses the following format for instructions

A
12
Q
A
13
Q

MIPS register positions?

A
14
Q

R-type instructions

A
15
Q

I-Type Instructions?

A
16
Q

Sign extension MIPS

A
17
Q

J-type instructions

A
18
Q

What makes MIPS a load/store register file approach?

A
19
Q

Issues with MIPS memory?

A
20
Q

MIPS memory types

A
21
Q

MIPS microprocessor datapath

A
22
Q

MIPS program counter

A
23
Q

MIPS Instruction memory and data memory:

A
24
Q

MIPS Registers:

A
25
Q

MIPS ALU?

A
26
Q

Example of datapath for instruction: add R1, R2, R3 R-type instruction, uses 3 registers, 2 source registers and 1 destination register

A
27
Q

MIPS implements the fetch-execute cycle with 5 stages

A
28
Q

HighRISC layout

A

The microprocessor that you are developing has a reduced and simple set of instructions. We call it HighRISC microprocessor

29
Q

HighRISC Instruction set?

A
30
Q
A